1. Field of the Invention
The present invention relates to a circuit for providing a corrected duty cycle.
2. Description of the Related Art
Generally, a delay locked loop (DLL) is used in a synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), to perform synchronization between an internal clock signal and an external clock signal of the synchronous semiconductor memory device. When the external clock signal is inputted to the synchronous semiconductor memory device, a time delay occurs due to a clock skew between the external clock signal and the internal clock signal. Therefore, the DLL is employed in the synchronous semiconductor memory device for generating the internal clock signal by compensating for the clock skew.
The DDR SDRAM inputs and/or outputs data at rising and falling edges of the clock signal so as to increase the transmission speed of data. As the operational speed of the DDR SDRAM is increased, performance of the DDR SDRAM is greatly affected by performance of the DLL. Therefore, since design margin decreases with an increase of duty error, having a correct duty cycle of the internal clock is important. Reliable data transmission is achieved when the duty cycle is equivalent to 50%, and a duty cycle correction method applied to the DLL is required for ensuring a sufficient design margin of the duty cycle.
FIG. 1 shows a prior art duty cycle correction circuit 10 disclosed in U.S. Pat. No. 8,106,697. The duty cycle correction circuit 10 comprises a duty cycle detector 11, a filter 12, an operational amplifier 13, a charge pump 14, a control circuit 15, and a duty cycle corrector 16. The duty cycle detector 11 receives a pair of internal clock signals CK and CKB and generates a pair of control signals DCF and DCFB. The filter 12 obtains average voltages of the pair of control signals DCF and DCFB. The amplifier 13 compares output voltages of the filter 12 and generates an enable signal EN. The control circuit 15 receives the enable signal EN and generates two switch enable signals ENCPS and ENCPL. The charge pump 14 receives the enable signals EN, ENCPS, and ENCPL and generates a pair of control signals DCC, DCCB. The duty cycle corrector 16 receives a pair of external clock signals ECK and ECKB, the two pairs of control signals DCF, DCFB, DCC, and DCCB and generates the pair of the internal clock signals CK and CKB with a corrected duty cycle of about 50%.
Referring to FIG. 1, the duty cycle correction circuit 10 requires the charge pump 14 to obtain the pair of control signals DCC, DCCB so as to correct the duty cycle of the external clock signals ECK and ECKB. However, the charge pump 14 has a speed limitation on the maximum operation frequency, which results in long duty cycle correction time. In addition, the duty cycle correction circuit 10 lacks a means of tracking the frequency variation of the input clock signal. Therefore, it may not be operated over a wide range of input frequencies.
Accordingly, there is a need to provide a circuit to solve the above problems.